1. Technical Field
The present invention relates to integrated circuit designs in general, and, in particular, to a method and apparatus for designing integrated circuits. Still more particularly, the present invention relates to a method and apparatus for performing input/output floor planning on an integrated circuit design.
2. Description of Related Art
For optimal input/output (I/O) circuit placement, I/O floor planning is typically driven by both physical placement constraints and electrical placement constraints. Physical placement constraints dictate the valid locations on silicon at which an on-chip/off-chip driver or receiver can be placed. Examples of physical placement constraints range from space congestion caused by existing macro or clock tree placement to valid voltage regions for supporting rail voltages of an I/O circuit. Using a variety of physical placement constraints, an I/O floor planning tool, such as ChipBench, can determine valid voltage regions at which I/O circuits can be placed within an integrated circuit.
Electrical placement constraints dictate the amount of I/O circuit clusters that can be supported within a small local region. Examples of electrical placement constraints may include maximum allowable average currents (Iavg) for preventing electromigration, maximum allowable rate of change in current (di/dt) for preventing excessive rail collapse, and maximum allowable peak current (Ipeak) for preventing excessive IR loss on a power rail. In order to evaluate whether an electrical placement constraint has been violated, an I/O floor planning tool estimates the Iavg, di/dt, and Ipeak values resulting from all the I/O circuits within an I/O circuit cluster and then compares the estimated Iavg, di/dt, and Ipeak values to the corresponding electrical placement constraints. If the estimated Iavg, di/dt, and Ipeak values exceed the corresponding electrical placement constraints, the I/O circuit cluster is considered as not electrically viable and needed to be modified, typically, by reducing the number of I/O circuits within the I/O circuit cluster.
Historically, the Iavg, di/dt, and Ipeak values used for each I/O driver have not considered the environment in which the I/O driver will operate. These values are supplied to the I/O floor planning tool as fixed values obtained using a “figure of merit” environment that may differ significantly from the customer's environment. A customer's environment is defined by the customer's off-chip loading conditions, the customer's operating temperature and voltages, and the package type. The difference between the customer's actual environment and the “figure of merit” environment assumed when determining fixed values for Iavg, di/dt, and Ipeak for each I/O circuit can cause those values to be either extremely conservative, which results in an increased turn around time during I/O floor planning, or extremely optimistic, which results in loss of performance or even chip failure.
Consequently, it would be desirable to provide an improved method for determining the Iavg, di/dt, and Ipeak values for I/O circuits within an integrated circuit design during the floor planning phase of the integrated circuit design.